GLOSSARY

KEY ROADMAP TECHNOLOGY CHARACTERISTICS TERMINOLOGY

(WITH OBSERVATIONS AND ANALYSIS)

CHARACTERISTICS OF MAJOR MARKETS

Technology Node—The minimum half-pitch of custom-layout (i.e., with staggered contacts/vias) metal interconnect is most representative of the process capability enabling high-density (low cost/function) integrated circuits and is selected to define an ITRS Technology Node. For each Node, this defining metal half-pitch is taken from whatever product has the minimum value. Historically, DRAMs have had leadership on metal pitch, but this could potentially shift to another product in the future.

Other parameters are also important for characterizing IC technology. For example, in the case of microprocessors (MPUs), physical bottom gate length is most representative of the leading-edge technology level required for maximum performance. Each technology node step represents the creation of significant technology progress in metal half-pitch — approximately 70% of the preceding node, 50% of two preceding nodes.

Example: DRAM half pitches of 180 nm, 130 nm, 90 nm, 65 nm, 45 nm, 32 nm, and 22 nm.

For cost reasons, high-volume, low-cost ASIC gate-length requirements will typically match DRAM half-pitch targets, but the low-volume leading-edge high-performance ASIC gate-length requirements will track closely with MPUs.

An official 2003 ITRS metal half-pitch node indicator, “hpXX,” has been added to differentiate the ITRS definition from commercial technology generation numbers .

Moore’s Law—An historical observation by Intel executive, Gordon Moore, that the market demand (and semiconductor industry response) for functionality per chip (bits, transistors) doubles every 1.5 to 2 years. He also observed that MPU performance [clock frequency (MHz) × instructions per clock = millions of instructions per second (MIPS)] also doubles every 1.5 to 2 years. Although viewed by some as a “self-fulfilling” prophecy, “Moore’s Law” has been a consistent macro trend and key indicator of successful leading-edge semiconductor products and companies for the past 30 years.

Cost-per-Function Manufacturing Productivity Improvement Driver—In addition to Moore’s Law, there is a historicallybased “corollary” to the “law,” which suggests that to be competitive manufacturing productivity improvements must also enable the cost-per-function (microcents per bit or transistor) to decrease by -29% per year. Historically, when functionality doubled every 1.5 years, then cost-per-chip (packaged unit) could double every six years and still meet the cost-per-function reduction requirement. If functionality doubles only every three years, as suggested by consensus

DRAM and MPU models of the 2003 ITRS, then the manufacturing cost per chip (packaged unit) must remain flat.

Affordable Packaged Unit Cost/Function—Final cost in microcents of the cost of a tested and packaged chip divided by Functions/Chip. Affordable costs are calculated from historical trends of affordable average selling prices [gross annual revenues of a specific product generation divided by the annual unit shipments] less an estimated gross profit margin of approximately 35% for DRAMs and 60% for MPUs. The affordability per function is a guideline of future market “topsdown” needs, and as such, was generated independently from the chip size and function density. Affordability requirements are expected to be achieved through combinations of—1) increased density and smaller chip sizes from technology and design improvements; 2) increasing wafer diameters; 3) decreasing equipment cost-of-ownership; 4) increasing equipment overall equipment effectiveness; 5) reduced package and test costs; 6) improved design tool productivity; and 7) enhanced product architecture and integration.

DRAM Generation at (product generation life-cycle level)—The anticipated bits/chip of the DRAM product generation introduced in a given year, manufacturing technology capability, and life-cycle maturity (Demonstration-level, Introduction-level, Production-level, Ramp-level, Peak). MPU Generation at (product generation life-cycle level)—The generic processor generation identifier for the anticipated Microprocessor Unit (MPU) product generation functionality (logic plus SRAM transistors per chip) introduced in a given year, manufacturing technology capability, and life-cycle maturity (Introduction-level, Production-level, Ramplevel, Peak).

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Cost-Performance MPU—MPU product optimized for maximum performance and the lowest cost by limiting the amount

of on-chip SRAM level-two (L2) cache (example 1Mbytes/2001). Logic functionality and L2 cache typically double

every three-year generation.

High-performance MPU—MPU product optimized for maximum system performance by combining a single or multiple

CPU cores (example two cores at 25Mt cores in 2001) with a large (example 4Mbyte/2001) level-two (L2) SRAM. Logic

functionality and L2 cache typically double every three-year technology generation by doubling the number of on-chip

CPU cores and associated memory.

Product inTER-generation—Product generation-to-generation targets for periodically doubling the on-chip functionality

at an affordable chip size. The targets are set to maintain Moore’s Law (2×/two years) while preserving economical

manufacturability (flat chip size and constant manufacturing cost per unit). This doubling every two years at a constant

cost assures that the cost/function reduction rate (inverse productivity improvement) is -29% per year (the target historical

rate of reduction). In order to double the on-chip functionality every two years, when technology-node scaling (.7× linear,

.5× area) is every three years, an additional device/process design improvement of .8× per two years must be achieved.

This requirement represents a design-related (cell-area-factor) area-reduction improvement of at least -11% per year, and

this design-related productivity improvement is in addition to the basic lithography-based area reduction of -21% per year

(three-year node cycle).

The present 2003 ITRS consensus target for the rate of increase of DRAM bits/chip has increased from 2× bits/chip every

two years to 2×/chip every two and half years average. This slower bits/chip growth is required due to the new consensus

2003 ITRS forecast of cell-area-factor improvement of only negative 4–6% per year on average rather than the 2001 ITRS

target of -7% per year average. This results in an average DRAM inTER-generation approximately flat chip-size growth.

Presently, the MPU transistor area is shrinking only at lithography-based rate (virtually no design-related improvement).

Therefore, the 2003 ITRS MPU inTER-generation functionality model target is 2× transistors/chip every technology node,

in order maintain a flat chip size growth throughout the roadmap period.

Product inTRA-generation—Chip size shrink trend within a given constant functions-per-chip product generation. The

2003 ITRS consensus-based model targets reduce chip size (by shrinks and “cut-downs”) utilizing the latest available

manufacturing and design technology at every point through the roadmap. The ITRS targets for both DRAM and MPU

reduce chip size within a generation by minus 50% per technology node.

Year of Demonstration—Year in which the leading chip manufacturer supplies an operational sample of a product as a

demonstration of design and/or technology node processing feasibility and prowess. A typical venue for the

demonstration is a major semiconductor industry conference, such as the International Solid State Circuits Conference

(ISSCC) held by the Institute of Electrical and Electronic Engineers (IEEE). Demonstration samples are typically

manufactured with early development or demonstration- level manufacturing tools and processes. Historically, DRAM

products have been demonstrated at 4× bits-per-chip every four years at the leading-edge process technology node,

typically two–three years in advance of actual market introduction. DRAM demonstration chip sizes have doubled every

eight years, requiring an increasing number of shrinks and delay before market introduction is economically feasible.

Frequently, chip sizes are larger than the field sizes available from lithography equipment, and must be “stitched”

together via multiple-exposure techniques that are feasible only for very small quantities of laboratory samples.

Example: 1997/ISSCC/1Gb DRAM, versus ITRS 1Gb 1999 Introduction-level, 2003 Production-level targets.

Year of INTRODUCTION—Year in which the leading chip manufacturer supplies small quantities of engineering samples

(<1K). These are provided to key customers for early evaluation, and are manufactured with qualified production tooling

and processes. To balance market timeliness and economical manufacturing, products will be introduced at 2×

functionality per chip every two years (every technology node, in the case of MPUs). In addition, manufacturers will

delay production until a chip-size shrink or “cut-down” level is achieved which limits the inTER-generation chip-size

growth to be flat.

Year of PRODUCTION—Year in which at least one leading chip manufacturer begins shipping volume quantities

(initially, at least 10K/month) of product manufactured with customer product qualified* production tooling and

processes and is followed within three months by a second manufacturer. (*Note: Start of actual volume production ramp

may vary between one to twelve months depending upon the length of the customer product qualification). As demand

increases for the leading-edge performance and shrink products, the tooling and processes are being quickly “copied” into

multiple modules of manufacturing capacity.

For high-demand products, volume production typically continues to ramp to fab design capacity within twelve months.

Alpha-level manufacturing tools and research technology papers are typically delivered 24–36 months prior to volume

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production ramp. Beta-level tools are typically delivered 12-24 months prior to ramp, along with papers at industry

conferences. The beta-level tools are made production-level in pilot-line fabs, which must be ready 12–24 months prior to

Production Ramp “Time Zero” [see Figure 2 in the Executive Summary] to allow for full customer product qualification.

The production-level pilot line fabs may also run low volumes of product that is often used for customer sampling and

early qualification prior to volume production ramp. Medium-volume production-level DRAMs will be in production

concurrently with low-volume introduction-level DRAMs, and also concurrently with very-high-volume, shrunken,

previous-generation DRAMs (example: 2003: 1Gb/production, 4G/introduction, plus 512Mb/256Mb/128Mb/64Mb highvolume).

Similarly, high-volume cost-performance MPUs are in production concurrently with their lower-volume, largechip,

high-performance MPU counterparts, and also with very-high volume shrinks of previous generations.

Functions/Chip—The number of bits (DRAMs) or logic transistors (MPUs/ASICs) that can be cost-effectively

manufactured on a single monolithic chip at the available technology level. Logic functionality (transistors per chip)

include both SRAM and gate-function logic transistors. DRAM functionality (bits per chip) is based only on the bits

(after repair) on a single monolithic chip.

Chip Size (mm2)—The typical area of the monolithic memory and logic chip that can be affordably manufactured in a

given year based upon the best available leading-edge design and manufacturing process. (Estimates are projected based

upon historical data trends and the ITRS consensus models).

Functions/cm2—The density of functions in a given square centimeter = Functions/Chip on a single monolithic chip

divided by the Chip Size. This is an average of the density of all of the functionality on the chip, including pad area and

wafer scribe area. In the case of DRAM, it includes the average of the high-density cell array and the less-dense

peripheral drive circuitry. In the case of the MPU products, it includes the average of the high-density SRAM and the

less-dense random logic. In the case of ASIC, it will include high-density embedded memory arrays, averaged with less

dense array logic gates and functional cores. In the 2003 ITRS, the typical high-performance ASIC design is assumed to

have the same average density as the high-performance MPUs, which are mostly SRAM transistors.

DRAM Cell Array Area Percentage—The maximum practical percentage of the total DRAM chip area that the cell array

can occupy at the various stages of the generation life cycle. At the introduction chip size targets, this percentage must be

typically less than 70% to allow space for the peripheral circuitry, pads, and wafer scribe area. Since the pads and scribe

area do not scale with lithography, the maximum cell array percentage is reduced in other inTRA-generation shrink levels

(typically less than 63% at the production level, and less than 50–55% for smaller previous generation shrunk die at the

high-volume ramp level).

DRAM Cell Area (µm2)—The area (C) occupied by the DRAM memory bit cell, expressed as multiplication of a specified

ITRS-consensus cell area factor target (A) times the square of the minimum half-pitch feature (f) size, that is: C = Af2. To

calculate the chip size, the cell area must be divided by the array efficiency, a factor (E) that is statistically derived from

historical DRAM chip analysis data. Thus an average cell area (CAVE) can be calculated, which is burdened by the

overhead of the drivers, I/O, bus lines, and pad area. The formula is: CAVE = C/E.

The total chip area can then be calculated by multiplying the total number of bits/chip times the CAVE.

Example: 1999: A=8; square of the half-pitch, f2= (180 nm)2=.032 µm2; cell area, C=Af2=0.26 µm2; for 1 Gb

introduction-level DRAM with a cell efficiency of E=70% of total chip area, the CAVE =C/E=0.37 µm2; therefore, the

1 Gb Chip Size Area=230 bits * 0.37e-6 mm2/bit = 397 mm2.

DRAM Cell Area Factor—A number (A) that expresses the DRAM cell area (C) as a multiple of equivalent square halfpitch

(f) units. Typically, the cell factor is expressed by equivalent aspect ratios of the half-pitch units (2×4=8, 2×3=6,

2×2=4, 1.6×1.6=2.5, etc.).

SRAM Cell Area Factor—Similar to the DRAM area factor, only applied to a 6-transistor (6t) logic-technology latch-type

memory cell. The number expresses the SRAM 6t cell area as a multiple of equivalent square technology-node half-pitch

(f) units. Typically, the cell factor of the SRAM 6t cell is 16–25 times greater than a DRAM memory cell area factor.

Logic Gate Cell Area Factor—Similar to the DRAM and SRAM cell area factors, only applied to a typical 4-transistor

(4t) logic gate. The number expresses the logic 4t gate area as a multiple of equivalent square technology-node half-pitch

(f) units. Typically, the cell factor of the logic 4t gate is 2.5–3 times greater than an SRAM 6t cell area factor, and 40–80

times greater than a DRAM memory cell area factor.

Usable Transistors/cm2 (High-performance ASIC, Auto Layout)—Number of transistors per cm2 designed by automated

layout tools for highly differentiated applications produced in low volumes. High-performance, leading-edge, embeddedarray

ASICs include both on-chip array logic cells, as well as dense functional cells (MPU, I/O, SRAM, etc). Density

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calculations include the connected (useable) transistors of the array logic cells, in addition to all of the transistors in the

dense functional cells. The largest high-performance ASIC designs will fill the available production lithography field.